The present invention relates generally to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device for preventing a decrease in the current applied to vertical PN diodes serving as cell switching elements in a cell region and a method for manufacturing the same.
Typical memory devices largely fall into the category of volatile random access memory (RAM), in which inputted information is lost when power is interrupted, and non-volatile read-only memory (ROM), in which the stored state of information can be maintained even when power is interrupted. Examples of volatile RAM include dynamic RAM (DRAM) and static RAM (SRAM), and examples of non-volatile ROM include flash memory devices, such as an electrically erasable and programmable ROM (EEPROM).
DRAM is generally considered an excellent memory device; however, DRAM must have a high charge storing capacity, which can be realized by increasing the surface area of an electrode. However, increasing the surface area of an electrode leads to difficulty in accomplishing a high level of integration. Further, in a flash memory device, two gates are stacked on each other, and therefore an operation voltage that is high in comparison to the power supply voltage is necessary. As such, in a flash memory device a separate booster circuit is needed to generate the voltage necessary for write and delete operations, which in turn leads to difficulty in accomplishing a high level of integration.
These constraints are often problematic, as the semiconductor industry continues to drive for a memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device. One example of a memory device considered as having potential is the phase change memory device. In the phase change memory device, a phase change layer is interposed between a bottom electrode and a top electrode. In order to store information, in the phase of the phase change layer can be changed between a crystalline state and an amorphous state by causing current to flow between the bottom electrode and the top electrode. The electrical resistivity of the amorphous state and the crystalline state are different, and therefore the information stored in a cell can be recognized, for example, by comparing the resistance of the phase change layer to the medium of the difference in resistance between the crystalline state and the amorphous state.
One of the most important factors that must be considered when developing a phase change memory device is the reduction of programming current. In this regard, recently developed phase change memory devices employ vertical PN diodes, which have a high degree of current flow, as cell switching elements in place of NMOS transistors. Because current flow can be increased and the size of cells can be decreased by employing the vertical PN diodes, it is possible to realize a highly integrated phase change memory device.
However, in a conventional phase change memory device employing vertical PN diodes, problems occur since undesired parasitic PNP bipolar junction transistors are formed between the vertical PN diodes and a p-well of the substrate, and thus current is not entirely transmitted to a phase change layer and can leak to the p-well.
In detail, FIG. 1 is a cross-sectional view for illustrating a conventional phase change memory device in which vertical PN diodes are used as cell switching elements and undesired parasitic PNP bipolar junction transistors are formed. Referring to FIG. 1, a high voltage is applied from a bit line 130 to a vertical PN diode 110, and a low voltage that is lower than the voltage applied to the vertical PN diode 110 is applied through a word line 132. As such, electrons flow from the word line 132 functioning as a low voltage terminal to a phase change layer 114 functioning as a high voltage terminal. The flow of electrons causes the temperature of the phase change layer 114 to change so that a phase change occurs in the phase change layer 114.
However, an undesired parasitic PNP bipolar transistor is created between the vertical PN diode 110 and a p-well 102. As a consequence, the electrons discharged from the low voltage terminal do not entirely flow to the vertical PN diode 110 and flow also to the p-well 102. Accordingly, when the conventional phase change memory device operates, current efficiency deteriorates.
In FIG. 1, reference numeral 100 designates a semiconductor substrate, 106 a well pick-up, 134 a metal line which includes the contact plug connected to the well pick-up 106, 104 an N+ base area, 112 a bottom electrode, and 116 a top electrode.
FIG. 2 is a graph shown for explaining the current loss in the conventional phase change memory device caused by the undesired parasitic PNP bipolar transistor. In the graph, ‘line a’ indicates the current flowing to the phase change layer when the bias of the p-well is grounded to 0V, and ‘line b’ indicates the current flowing to the phase change layer when the p-well is floated such that current cannot flow to the p-well.
When referring to the graph, it can be appreciated that there is a difference in the amount of current flow between the case in which the bias of the p-well is grounded to 0V and the case in which the p-well is floated. The difference in the amount of current flow corresponds to the amount of current which discharges through the p-well.
Therefore, as shown the efficiency of operation current in the conventional phase change memory device which adopts the vertical PN diodes as cell switching elements is decreased by the by the undesired parasitic PNP bipolar transistor.